1. Field
The present disclosure relates to a technique for memory access, and specifically to memory access utilizing internet protocol (IP) addressing semantics.
2. Background Information
Currently, the market is driving larger physical and virtual address space on commodity hardware as exemplified by the EM64T and AMD64 extensions to the x86 instruction set. Also, the High Performance Computing (HPC) community is increasingly moving towards clusters of commodity systems typically connected via a high-speed interconnect. Such interconnects may include Infiniband or Quadrics technology.
Typically, these clusters or distributed computing systems need to communicate with other systems within and without the cluster. Often various process within a program running on the cluster need to communicate or provide data to another process within the program. Such Inter-Process Communication (IPC) incurs a large overhead. Unfortunately, there is currently no widely used standard messaging mechanism for IPC in large systems, beyond massive SMP's that cost a large amount of money to maintain cache-coherence.
Often scientific HPC applications may be coded utilizing the Message Passing Interface (MPI) library in order to gain some degree of portability. However, there is invariably some layer of software that must bind to the particular interconnection transport. Therefore, it would be beneficial for HPC deployments to have a low-latency IPC mechanism. Preferably the mechanism would be highly portable and available via commodity hardware. It is understood that, while any such mechanism may be advantageous for HPC systems, such a mechanism may also be useful to peer-to-peer gaming and other emergent network use-models.